Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems

Article / Book Information 論題(和文) Title(English) Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems 著者(和文) 稲木 雅人, 高島 康裕, 中村 祐一, 高橋 篤司 Authors(English) Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi 出典(和文) , Vol. E91-A, No. 12, pp. 3539-3547 Citation(English) IEICE Trans. Fundamentals, Vol. E91-A, No. 12, pp. 3539-3547 発行日 / ...

Performance Driven Inter-FPGA Synchronization Algorithm for Multi-FPGA Simulation Accelerator with Event Time-multiplexing Bus

Simulation is the most viable solution for the functional verification of SoC. The acceleration of simulation with multi-FPGA is a promising method to comply with the increasing complexity and large gate capacity of SoC. The most time-consuming factor of multi-FPGA simulation accelerator is synchronization time between simulator and multi-FPGA system. Time-multiplexing of interconnection wires ...

Multi - FPGA Systems

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